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INTEGRATED CIRCUITS
DATA SHEET
SAA7710T Dolby* Pro Logic Surround; Incredible Sound
Product specification Supersedes data of 1997 Oct 03 File under Integrated Circuits, IC01 1998 Mar 13
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
FEATURES * Two stereo I2S-bus digital input channels * Three stereo I2S-bus digital output channels * I2C-bus mode control * Up to 45 ms on-chip delay-line (fs = 44.1 kHz) * Optional clock divider for crystal oscillator * Package: SO32L * Operating supply voltage range: 4.5 to 5.5 V. Functions * 4-channel active surround, 20 Hz to 20 kHz (maximum 12fs) * Adaptive matrix * 7 kHz low-pass filters * Adjustable delay for surround channel * Modified Dolby B noise reduction * Noise sequencer * Variable output matrix * Sub woofer * Centre mode control: on/off, normal, phantom, wide * Output volume control * Automatic balance and master level control with DC-offset filter QUICK REFERENCE DATA SYMBOL VDD VDD Vi IDD ISS Tamb Tstg PARAMETER DC supply voltage voltage difference between two VDDx pins maximum input voltage DC supply current DC supply current ambient operating temperature storage temperature range MIN. -0.5 - -0.5 - - -40 -65
SAA7710T
* Hall/matrix surround sound functions * Incredible sound functions * 5-band parametric equalizer on main channels left, centre, right (fs = 32 kHz) * Tone control (bass/treble) on all four output channels (fs = 44.1 kHz). GENERAL DESCRIPTION This data sheet describes the 104 ROM-code version of the SAA7710T chip. The SAA7710T chip is a high quality audio-performance digital add-on processor for digital sound systems. It provides all the necessary features for complete Dolby Pro Logic surround sound on chip. In addition to the Dolby Pro Logic surround function, this device also incorporates a 5-band parametric equalizer, a tone control section and a volume control. Instead of Dolby Pro Logic surround, the Hall/matrix surround and Incredible sound functions can be used together with the equalizer or tone control.
MAX. +6.5 550 VDD + 0.5 50 50 +85 +150
UNIT V mV V mA mA C C
Remark Dolby*: Dolby' and `Pro Logic' are trademarks of Dolby Laboratories Licensing Corporation. They are available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, CA94111, USA, from whom licensing and application information must be obtained. ORDERING INFORMATION TYPE NUMBER SAA7710T/N104 PACKAGE NAME SO32 DESCRIPTION plastic small outline package; 32 leads; body width 7.5 mm VERSION SOT287-1
1998 Mar 13
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I2S_BCKIN1 I2S input 1 I2S_WSIN1 I2S_DATAIN1 22 23 24 SURROUND CHANNEL DELAY LINE I2S INPUT SWITCH CIRCUIT L DOLBY PRO LOGIC OR DOLBY 3 STEREO OR HALL/MATRIX OR INCREDIBLE SOUND C R SW 5-BAND PARAMETRIC EQUALIZER OR TONE CONTROL VARIABLE OUTPUT MATRIX I2S OUT 1 28 I2S outputs I2S_DATAOUT1 S I2S_DATAIN2 I2S input 2 I2S_BCKIN2 I2S_WSIN2 DSP_RESET 25 27 26 17 data 1
BLOCK DIAGRAM
Philips Semiconductors
handbook, full pagewidth
Dolby* Pro Logic Surround; Incredible Sound
2 1
I2S_BCKOUT I2S_WSOUT
SAA7710T
I2S OUT 2
29
I2S_DATAOUT2
I2S OUT 3
30
I2S_DATAOUT3
5 13 3 TEST + 12 + 32
VDD1 VDD2 VDD3
3
TSCAN RTCB
AUTO BALANCE FUNCTION
19 FLAG TEST CONTROL I2C BUS TRANSCEIVER OSCILLATOR 18 6 11 31 7 8 9 10 15 16 14 21 20 4
VDD_XTAL VSS_XTAL VSS1 VSS2 VSS3
Product specification
SAA7710T
DSP_IN1
DSP_OUT1 DSP_OUT2
SDA
SCL
A0
OSC
XTAL
SHTCB
MGE751
DSP_IN2
Fig.1 Block diagram.
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
PINNING SYMBOL I2S_WSOUT I2S_BCKOUT RTCB SHTCB VDD1 VSS1 DSP_IN1 DSP_IN2 DSP_OUT1 DSP_OUT2 VSS2 VDD2 TSCAN A0 SDA SCL DSP_RESET VSS_XTAL VDD_XTAL XTAL OSC I2S_BCKIN1 I2S_WSIN1 I2S_DATAIN1 I2S_DATAIN2 I2S_WSIN2 I2S_BCKIN2 I2S_DATAOUT1 I2S_DATAOUT2 I2S_DATAOUT3 VSS3 VDD3 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I2S-bus output I2S-bus slave bit-clock output asynchronous reset test control block input (active LOW) clock divider switch enable input (LOW = divide) positive power supply ground power supply flag input 1 flag input 2 flag output 1 flag output 2 ground power supply positive power supply scan control input I2C-bus slave address selection input I2C-bus serial data input/output I2C-bus serial clock input chip reset input (active LOW) ground power supply crystal oscillator positive power supply crystal oscillator crystal oscillator output crystal oscillator input I2S-bus master bit-clock input 1 I2S-bus master word-select input 1 I2S-bus master data input 1 I2S-bus master data input 2 I2S-bus master word-select input 2 I2S-bus master bit-clock input 2 I2S-bus slave data output 1 I2S-bus slave data output 2 I2S-bus slave data output 3 ground power supply positive power supply
handbook, halfpage I2S_WSOUT
SAA7710T
DESCRIPTION slave word-select
1 2 3 4 5 6 7 8
32 VDD3 31 VSS3 30 I2S_DATAOUT3 29 I2S_DATAOUT2 28 I2S_DATAOUT1 27 I2S_BCKIN2 26 I2S_WSIN2 25 I2S_DATAIN2
I2S_BCKOUT RTCB SHTCB VDD1 VSS1 DSP_IN1 DSP_IN2 DSP_OUT1
SAA7710T
9 DSP_OUT2 10 VSS2 11 VDD2 12 TSCAN 13 A0 14 SDA 15 SCL 16
MGE750
24 I2S_DATAIN1 23 I2S_WSIN1 22 I2S_BCKIN1 21 OSC 20 XTAL 19 VDD_XTAL 18 VSS_XTAL 17 DSP_RESET
Fig.2 Pin configuration.
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Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
FUNCTIONAL DESCRIPTION Figure 1 shows the block diagram of the SAA7710T. The SAA7710T consists of a Dolby Pro Logic decoder together with equalizer or tone control. The Dolby Pro Logic part of the IC may be used to decode audio soundtracks (Dolby surround movies or Dolby surround video productions) from for example, a video recorder (VCR) or a CD laser disc into four channels Left, Centre, Right and Surround (L, C, R and S). If desired, post-processing with either an equalizer or a tone control section is possible. In addition to this, a Sub Woofer (SW) channel, digital volume control and a user-programmable variable output matrix are implemented. Hall/matrix surround sound functions are implemented for material not encoded using Dolby Surround. These features can be used as an alternative to Dolby Pro Logic and can also be combined with the equalizer or tone control sections. Incredible sound is a Philips patented technology which substantially improves the stereo effect of a television or audio system. Using advanced signal processing, speakers that are positioned close together can imitate the sound produced by speakers that are far apart. Functional modes The device thus supports three main modes, Dolby Pro Logic/Dolby 3 stereo or hall/matrix surround or Incredible sound mode. All modes can be combined with equalizing (3-band or 5-band) or tone control depending on fs and available cycle budget. THE DOLBY PRO LOGIC MODE In Dolby Pro Logic mode, several blocks must be initialized and controlled during operation: * Noise generator and noise sequencer * Centre channel mode(1) (normal, phantom, wide, off) * Combining network coefficients * 7 kHz low-pass filter in surround channel(1) * Surround channel delay time(1) * Modified Dolby B noise reduction must be on. Possible post-processing modes for Dolby Pro Logic are: * Volume control only
(1) The coefficient set used to initialize and control the operation of the Dolby Pro Logic mode depends upon the selected sampling frequency fs = 32, 44.1 or 48 kHz.
SAA7710T
* Equalizer (3- or 5-band on L, C and R) or tone control (L, C, R and S); fixed output matrix(1); volume control * Equalizer (5-band on L, C and R); variable output matrix(1); volume control * Extra sub woofer(1). THE DOLBY 3 STEREO MODE In Dolby 3 stereo mode, several blocks must be initialized and controlled during operation: * Noise generator and noise sequencer * Centre channel mode(1) (normal, phantom, wide and off) * Combining network coefficients * Incredible Sound widening of the stereo base on two speakers * Effect is user adjustable. THE HALL/MATRIX SURROUND MODE In hall/matrix surround mode, the blocks listed below must be initialized and controlled during operation: * Input balance control * Hall or matrix surround Mode setting * All-pass and filter transfer characteristics(1) * 7 kHz low-pass filter in surround channel(1) * Surround channel delay(1). Possible post-processing modes for hall/matrix surround are as above: * Volume control only * Equalizer (5-band on L, C and R) or tone control (L, C, R and S); fixed output matrix(1); volume control * Equalizer (5-band on L,C,R); variable output matrix(1); volume control * Extra sub woofer(1). THE INCREDIBLE SOUND MODE In the Incredible sound mode the blocks listed below must be initialized and controlled during operation: * Incredible sound coefficients * Combining network coefficients. Possible post-processing modes for incredible sound are as follows: * Volume control only * Equalizer (5-band on L and R) or tone control (L and R); variable output matrix(1), volume control * Extra sub-woofer(1). 5
1998 Mar 13
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
ADDITIONAL INFORMATION The possible modes of operation are discussed in more detail in the "SAA7710T Dolby Pro Logic Programming Guide, Application Note AN95063". This also includes which features are available for a given system clock frequency and sample frequency and the possible input configurations. Clock circuit and oscillator The chip has an on board crystal clock oscillator. The block schematic of this Pierce oscillator is shown in Figs 3 and 4. The active element needed to compensate for the loss resistance of the crystal is the amplifier Gm. This amplifier is placed between the XTAL (output) pin and the OSC (sense) pin. The gain of the oscillator is internally controlled by the automatic gain control. This prevents too much power loss in the crystal. The higher harmonics are then as low as possible. The signals on the OSC and XTAL pin are differentially amplified. The oscillator has these two modes of operation: The crystal oscillator mode: in this mode (see Fig.3), a quartz crystal oscillator is used to generate a clock signal which is subsequently divided by 2 to ensure that the final clock signal has a 50% duty cycle. The oscillator circuit components Rbias and C1, C2 depend on the crystal. In the case of an overtone oscillator, the ground harmonic is filtered out by L1 and C3. Pin SHTCB is held low so that the divided signal is selected. Only a quartz crystal should be used in this mode.
SAA7710T
The slave oscillator mode: in this mode (see Fig.4), the oscillator circuit acts as a slave driven by a master system clock. The clock divider can be switched on or off using pin SHTCB. When the divider is not used, the duty cycle of the clock will depend on the master system clock duty cycle and the rising and falling edge times. This places a tolerance of 5% on the 50% duty cycle of the master system clock (see Chapter "AC characteristics"). In order to be able to control the phase of the clock signal during testing the divider is skipped and the signal is directly fed to the circuit via the multiplexer in the TEST position. SUPPLY OF THE CRYSTAL OSCILLATOR The power supply connections to the oscillator are separated from the other supply lines to minimise feedback from on-chip ground bounce to the oscillator circuit. Noise on the power supply affects the AGC operation so the power supply should be decoupled. The VSS_XTAL pin is used as ground supply and the VDD_XTAL as positive supply.
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Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
SAA7710T
handbook, full pagewidth
AGC
Gm
DIVIDE BY 2
0 1 TEST
CLOCK BUFFER
ON CHIP 21 OFF CHIP OSC 20 XTAL 19 VDD_XTAL 18 VSS_XTAL 4 SHTCB =0 100 k Rbias C1 10 pF C2 10 pF L1 4.7 H C3 1 nF
MGE752
Fig.3 Block diagram crystal oscillator circuit.
handbook, full pagewidth
AGC
Gm
DIVIDE BY 2
0 1 TEST
CLOCK BUFFER
ON CHIP 21 OFF CHIP OSC 100 k 20 XTAL 19 VDD_XTAL 18 VSS_XTAL 4 SHTCB =1
MGE753
40 pF
10 pF slave input
10 nF
Fig.4 Block diagram slave oscillator circuit.
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Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
I2S-bus Interfaces and system clock I2S-BUS BASICS
Tcy tLC0.35 T SCK tsr0.2 T SD WS thr0 VIH (70%) VIL (20%) tHC0.35 T
SAA7710T
handbook, full pagewidth
VIH (70%) VIL (20%)
SCK
WS
SD
MSB LEFT
MSB RIGHT
MBH173
Fig.5 I2S-bus timing and format.
For communication with external digital sources and or additional external processors the I2S-bus digital interface bus is used. It is a serial 3-line bus, with one line for data, one line for clock and one line for the word select. Figure 5 shows an excerpt of the Philips I2S-bus specification interface report regarding the general timing and format of I2S-bus. Word Select (WS) logic 0 means left channel word, logic 1 means right channel word. The serial data is transmitted in two's complement with the MSB first. One clock period after the negative edge of the word select line the MSB of the left channel is transmitted. Data is synchronised with the negative edge of the clock and latched at the positive edge.
I2S-BUS INPUT CIRCUIT The I2S-bus input circuits can be configured in the following way using the SEL-IN1/IN2 bit (see Table 4): 1. I2S input 1 is master (SEL-IN1/IN2 bit = logic 0(default)) 2. I2S input 2 is master (SEL-IN1/IN2 bit = logic 1). The incoming bit-clock frequency defines the accuracy in terms of number of bits of the incoming data samples. The input circuit is designed to accept any number of bits per channel up to a maximum of 18 bits. The accepted data format is MSB-first.
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Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
Table 1 Data Accuracy in I2S-bus Interface I2S-BUS IN DATA WIDTH A 18
SAA7710T
INCOMING DATA WIDTH A < 18 B 18 THE I2S-BUS OUTPUT INTERFACE
I2S-BUS OUT DATA WIDTH A 18
The I2S-bus data output interfaces (see Fig.1) I2S OUT 1, I2S OUT 2 and I2S OUT 3 use the same I2S-bus data signals which are selected by the input switch circuit. The I2S-bus WS and BCK output signals remain in phase with the external input signals at all times. The output data is 1/fs cycle delayed relative to the input data. The selected word-select and bit-clock are included as part of the output
interface: I2S_WSOUT, I2S_BCKOUT. These two output signals can be 3-stated by setting the DIS_BCKWS bit (see Table 4). The 3-state output of the I2S_DATAOUT3 signal can be enabled by setting the ENA_I2S3 bit (see Table 4). The timing diagram of the I2S-bus outputs is shown in Fig.6. The timing details can be found in Chapter "AC characteristics".
handbook, full pagewidth
tLC tHC td1 tr tf tf tr I2S_BCKIN1, 2 I2S_BCKOUT
CL
WS td2
I2S_WSIN1, 2 I2S_WSOUT
ts2 DATA (in)
DATA VALID td3 tr tf
MSB
I2S_DATAIN1, 2
tacc
DATA (out)
MSB
I2S_DATAOUT1, 2, 3
MGE755
Fig.6 Timing diagram of I2S-bus output interface.
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Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
I2C-bus control and commands CHARACTERISTICS OF THE I2C-BUS The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to the VDDX via a pull-up resistor when connected to the output stages of a microprocessor. Data transfer can only be initiated when the bus is not busy. BIT TRANSFER One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. The maximum clock frequency is 100 kHz (see Fig.7). START AND STOP CONDITIONS Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Fig.8). DATA TRANSFER
SAA7710T
A device generating a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves' (see Fig.9). ACKNOWLEDGE The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition (see Fig.10).
handbook, full pagewidth
SDA
SCL data line stable data valid change of data allowed
MLC160
Fig.7 Bit transfer on the I2C-bus.
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Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
SAA7710T
andbook, full pagewidth
SDA
SCL S START condition P STOP condition
MLC161
Fig.8 START and STOP conditions.
handbook, full pagewidth
SDA MSB acknowledgement signal from receiver byte complete interrupt within receiver clock line held LOW while interrupts are serviced 2 7 8 9 ACK 1 2 3 to 8 acknowledgement signal from receiver
SCL S
1
9 P STOP condition
MLC162
START condition
Fig.9 Data transfer on the I2C-bus.
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Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
SAA7710T
handbook, full pagewidth
data output from transmitter not acknowledge
data output from receiver acknowledge
SCL from master S
1
2
7
8
9
MLC163
START condition
clock pulse for acknowledgement
Fig.10 Acknowledge on the I2C-bus.
I2C-BUS FORMAT
Write cycles
The I2C-bus configuration for a write cycle is shown in Fig 12. The write cycle is used to write in the input selector control register and to initialise or update coefficient values. The data length is 2 bytes or 3 bytes depending of the accessed memory. If the Y-memory is addressed the data length is 2 bytes, in case of the X-memory the length is 3 bytes. The slave receiver detects the address and adjusts the bytes accordingly.
Addressing
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always done with the first byte transmitted after the START procedure.
Slave address (pin A0)
The chip acts as a slave receiver or a slave transmitter. Therefore the clock signal SCL is only an input signal. The data signal SDA is a bidirectional line. The chip slave address is shown in Table 2. The sub address bit A0 corresponds to the hardware address pin A0 which allows the device to have 1 of 2 different addresses.
Read cycles
The I2C-bus configuration for a Read cycle is shown in Fig 13. The read cycle is used to read data values from XRAM or YRAM.
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Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
I2C-BUS FUNCTION BITS
SAA7710T
During the write cycle, the I2C-bus clock frequency must be reduced. The I2C-bus clock frequency has the following constraints: fs > 2 x fIIC fs = I2S-bus sampling frequency fIIC = I2C-bus clock frequency. If this constraint cannot be met, a higher I2C-bus frequency can be obtained in the following way: By making the I2C-bus master insert a delay (td) after the acknowledge pulse (see Fig.11). The delay should be larger than or equal to 1/fs where fs is the I2S-bus sampling frequency. By not using the auto-increment feature. This means that each data word must be preceded by its intended destination address.
Input selector control register
The write only, two byte, input selector control register is located on absolute address 0FFFH (4095) and consists of 16 bits, starting with bit 0 and ending with bit 15.
Deviation from the I2C-bus specification
1. The data hold time (tHD;DAT) for this device (0 ns as stated in the I2C-bus specification) should be as follows: a) For the crystal oscillator mode (SHTCB = 0): 6 --------- f xtal b) For the slave oscillator mode (SHTCB = 0): 6 ------------ f slave c) For the slave oscillator mode (SHTCB = 1): 3 ------------ f slave
handbook, full pagewidth
SCL
SDA
ACKNOWLEDGE AFTER WORD auto-increment address register
td
MGE756
Fig.11 Timing of reduced I2C-bus frequency.
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Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
Table 2 Slave address
SAA7710T
MSB 0 Table 3 MSB DATAH 15 Note 1. Explanation for the contents of the register bits: a) A = standard I2C-bus acknowledge. b) Number = bit number according to Table 4. c) P = standard I2C-bus STOP condition. Table 4 Input selector control bits FUNCTION I2S input 1 or I2S input 2 input disable enable I2S_BCKOUT and I2S_WSOUT I2S_DATAOUT3 NUMBER OF BITS 1 1 1 1 ON RESET IN1(0) enable(0) disable(0) resets(0) 14 13 12 11 10 9 8 A 7 6 5 DATAL 4 3 2 1 0 0 1 1 1 1 A0
LSB R/W
Location of input selector control register bits in I2C-bus serial transmission; note 1 LSB
A
P
SYMBOL SEL-IN1/IN2 DIS_BCKWS ENA-I2S3 IMODE
BIT NO 5 7 13 15
I flag resets/background tasking
XRAM format
The XRAM block consists of 256 18-bit RAM locations 0 to 255 and is located on the absolute address range of 0000H to 00FFH. The I2C-bus transfer consists of 18 useful bits out of 24 bits. Table 5 MSB DATAH D Note 1. Explanation for the contents of the register bits: a) D = contents of I2C-bus data register bit is don't care. b) A = standard I2C-bus acknowledge. c) Number = bit number being useful bit XRAM memory. d) P = standard I2C-bus STOP condition. D D D D DATAM D 17 16 A 15 14 13 12 11 10 9 8 A 7 6 5 DATAL 4 3 2 1 0 A P Format XRAM bits; note 1 LSB
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Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
YRAM format
SAA7710T
The YRAM block consists of 256 12-bit RAM locations 0 to 255 and is located on the absolute address range of 0800H to 08FFH. The I2C-bus transfer consists of 12 useful bits out of 16 bits. Table 6 MSB DATAH D Note 1. Explanation for the contents of the register bits: a) D = contents of I2C-bus data register bit is don't care. b) A = standard I2C-bus acknowledge. c) Number = bit number being useful bit XRAM memory. d) P = standard I2C-bus STOP condition. D D D 11 10 9 8 A 7 6 5 DATAM 4 3 2 1 0 A P Format YRAM bits; note 1 LSB
Error processing
If a read action is done without first initialising the memory address the acknowledge after the read command will not be generated by the chip. This should be treated as an error message: Table 7 S Write ACK ADDRH ACK ADDRL ACK S Read S Read NEG ACK Correct read sequence Incorrect read sequence; address is not initialized
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A
Philips Semiconductors
Dolby* Pro Logic Surround; Incredible Sound
S 0 0 1 1 1 1 A0 0 C
K
ADDR H
A C K
ADDR L
A C K
DATA H
A C K
DATA M
A C K
DATA L
A CP K
auto increment if repeated n-groups of 3 (2) bytes address R/W
MBH529
Fig.12 Master transmitter writes to chip. 16
A
S 0 0 1 1 1 1 A0 0 C
K
ADDR H
A C K
ADDR L
A A C S 0 0 1 1 1 1 A0 1 C K K
DATA H
A C K
DATA M
A C K
DATA L
A CP K
auto increment if repeated n-groups of 3 (2) bytes address R/W R/W
MBH528
Product specification
SAA7710T
Fig.13 Master transmitter reads from chip.
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
DSP_RESET The DSP_RESET pin is active LOW and has an internal pull-up resistor. To enable a proper switch-on of the supply voltage a capacitor should be connected between this pin and VSS. The capacitor value is such that the chip is in a reset state as long as the power supply is not stabilized. The DSP_RESET has the following functions: * The bits of the input selector control register are set to logic 0 (see Table 4) * The program counter is set to address 0000H * The I2C-bus interface is initialised; the SDA pin is guaranteed high-impedance.
SAA7710T
When the level on the DSP_RESET pin is HIGH, the DSP program starts to run. When the level on the DSP_RESET pin is low, the SDA pin is asynchronously set to a high-impedance state. In the absence of a clock and during the power-up reset, the SDA line is high-impedance. TEST MODE CONNECTIONS (TSCAN, RTCB AND SHTCB
PINS)
The TSCAN, RTCB and SHTCB pins are used to put the chip in test mode and to test the internal connections. Each pin has an internal pull-down resistor to ground. In the application these pins can be left open-circuit or connected to ground.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC134). SYMBOL VDD VDD Vi(max) lIK lOK lO lDD lDD lSS VESD PARAMETER DC supply voltage voltage difference between two VDDx pins maximum input voltage DC input clamp diode current DC output clamp diode current output type 4 mA DC output source or sink current output type 4 mA DC output source or sink current output type 4 mA DC VDD supply current per pin DC VSS supply current per pin ESD sensitivity for all pins human body model machine model all pins except pin OSC machine model pin OSC LTCH Ptot Tamb Tstg latch-up protection total power dissipation operating ambient temperature storage temperature 100 pF; 1500 200 pF; 2.5 H; 0 200 pF; 2.5 H; 0 CIC spec/test method 3000 300 250 100 - -40 -65 - - - - 700 +85 +150 V V V mA mW C C Vi < -0.5 V or Vi > VDD + 0.5 V Vo < -0.5 V or Vo > VDD + 0.5 V -0.5 V < Vo < VDD + 0.5 V -0.5 V < Vo < VDD + 0.5 V CONDITIONS - -0.5 - - - - - - MIN. -0.5 MAX. +6.5 550 10 20 20 20 50 50 UNIT V mV mA mA mA mA mA mA
VDD + 0.5 V
THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER thermal resistance from junction to ambient in free air VALUE 57 UNIT K/W
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Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
SAA7710T
DC CHARACTERISTICS VDD1 = VDD2 = VDD3 = VDD_XTAL = 4.5 to 5.5 V; Tamb = -40 to +85 C; note 1; unless otherwise specified. SYMBOL VDDtot IDD(tot) Ptot VIH VIL Vhys VOH VOL ILI ILO Rpu(VDDX)(int) Rpd(VSSD)(int) PARAMETER total DC supply voltage total DC supply current total power dissipation HIGH level input voltage all digital inputs and I/Os LOW level input voltage all digital inputs and I/Os hysteresis voltage HIGH level output voltage digital outputs LOW level output voltage digital outputs input leakage current output leakage current 3-state outputs internal pull-up resistor to VDDX internal pull-down resistor to VSSD positive supply voltage crystal oscillator DSP frequency = 18 MHz; maximum activity DSP DSP frequency = 18 MHz; maximum activity DSP pin types I1, I2 and I3 pin type I4 pin types I1, I2 and I3 pin type I4 pin type I4 VDDX = 4.5 V; Io = -4 mA; pin type O1 and O2 VDDX = 4.5 V; Io = 4 mA; pin types I3, O1 and O2 Vi = 0 or VDDX voltage; pin type I1 Vo = 0 or VDDX voltage; pin type I3 and O2 pin type I4 pin type I2 CONDITIONS - - 0.7VDDX 0.8VDDX - - - 4.0 - - - 17 17 MIN. 4.5 5 50 250 - - - - - - - - - - TYP. MAX. 5.5 55 300 - - 0.3VDDX 0.2VDDX - 0.5 1 5 134 134 V mA mW V V V V V V V A A k k UNIT
0.33VDDX -
Crystal oscillator VDDX Note 1. VDDX = VDD_XTAL. 4.5 5 5.5 V
1998 Mar 13
18
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
AC CHARACTERISTICS VDD1 = VDD2 = VDD3 = VDD_XTAL = 4.5 to 5.5 V; Tamb = 25 C; unless otherwise specified. SYMBOL fxtal f Ixtal gm(XTAL) Vxtal CL(XTAL) Rxtal PARAMETER crystal frequency CONDITIONS see Fig.3 - 20 - 4 - - - MIN. TYP. - - 500 8 500 25 20 - - - - - 60
SAA7710T
MAX. 36.864
UNIT MHz dB A mS mV pF
spurious frequency attenuation current through crystal at input voltage swing 0.2 V transconductance voltage across crystal load capacitance allowed loss resistor of crystal at start-up note 1 Cp = 5 pF; C1 = 10 pF; C2 = 10 pF no divider; see Fig.4 see Fig.4 0.1 to 0.9VDD_XTAL; note 2 0.1 to 0.9VDD_XTAL; note 2
Slave oscillator fslave SLVOLT tr tf Timing I2C-BUS INPUTS/OUTPUT tf fi(max) tr tf tHC tLC td1 td2 ts2 td3 tacc tr tf
ALL OTHER
slave frequency slave drive voltage input rise times input fall times
- 3.75 - -
- - - -
18.432 - 20 20
MHz V ns ns
fall time I2C-bus maximum input frequency rise time I2S-bus (O2) fall time I2S-bus (O2) CL pulse width HIGH CL pulse width LOW WS out delay time data in hold time data in set-up time data out delay time data out access time (O1) rise time fall time INPUTS input rise times input fall times
0.1 to 0.9VDD SDA, SCL CL = 30 pF; 0.1 to 0.9VDD CL = 30 pF; 0.1 to 0.9VDD
- - - - 112 112 0 0 25 0 -
5.7 - 7.3 8.3 - - - - - - - 7.3 8.3 6 6
- 100 - - - - - - - 5 5 + 0.5 x CL(3) - - 200 200
ns kHz ns ns ns ns ns ns ns ns ns ns ns ns ns
I2S-BUS INPUTS/OUTPUTS
ALL OTHER OUTPUTS
CL = 30 pF; 0.1 to 0.9VDD CL = 30 pF; 0.1 to 0.9VDD VDD = 5.5 V VDD = 5.5 V
- - - -
tr tf Notes
1. The load capacitance is the sum of the series connection of C1 and C2 (see Fig.3) and the parasitic parallel capacitor of the crystal Cp. 2. With a 50%, 5% duty cycle on oscillator drive input (see Fig.4). 3. The value for the capitative load CL is given in pF.
1998 Mar 13
19
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
INTERNAL CIRCUITRY PIN 7 8 16 22 23 24 25 26 27 17 SYMBOL DSP_IN1 DSP_IN2 SCL I2S_BCKIN1 I2S_WSIN1 I2S_DATAIN1 I2S_DATAIN2 I2S_WSIN2 I2S_BCKIN2 DSP_RESET PIN TYPE I1 I1 I1 I1 I1 I1 I1 I1 I1 I4
7, 8, 16, 22, 23, 24, 25, 26, 27
SAA7710T
DC VOLTAGE (V)
INTERNAL CIRCUIT
MGE758
17
+
MGE759
3 4 13 14
RTCB SHTCB TSCAN A0
I2 I2 I2 I1
MGE760
3, 4, 13, 14
1 2 9 30
I2S_WSOUT I2S_BCKOUT DSP_OUT1 I2S_DATAOUT3
O2 O2 O2 O2
MGE761
1, 2, 9, 30
1998 Mar 13
20
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
PIN 15 SYMBOL SDA PIN TYPE I3 DC VOLTAGE (V)
SAA7710T
INTERNAL CIRCUIT
15
MGE762
10 28 29
DSP_OUT2 I2S_DATAOUT1 I2S_DATAOUT2
O1 O1 O1
10, 28, 29
MGE763
5 6 11 12 31 32 21 20 19 18
VDD1 VSS1 VSS2 VDD2 VSS3 VDD3 OSC XTAL VDD_XTAL VSS_XTAL
tbf 0 0 5 0 5 tbf tbf 5 0
20 21 19
18
MGE764
1998 Mar 13
21
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I2S input 1 I2S input 2 220 pF 220 220 220 pF I2S_WSIN2 26
APPLICATION INFORMATION
Philips Semiconductors
handbook, full pagewidth
Dolby* Pro Logic Surround; Incredible Sound
220
220 220 pF
I2S_BCKIN1 22
2 I2S_BCKOUT
220
220 220 pF
220
220 220 pF
I2S_WSIN1 23
1 I2S_WSOUT
220
220 220 pF
SAA7710T
S SURROUND CHANNEL DELAY LINE I2S INPUT SWITCH CIRCUIT I2S OUT 1 5-BAND PARAMETRIC EQUALIZER OR TONE CONTROL 28 I2S_DATAOUT1 220
220
220 I2S_DATAIN1 24 220 pF
220
220 I2S_DATAIN2 25 220 pF
I2S outputs 220 220 pF VARIABLE OUTPUT MATRIX I2S OUT 2 29 I2S_DATAOUT2 220 220 220 pF I2S OUT 3 30 I2S_DATAOUT3 220 220 220 pF 5 VDD1 100 nF 12 VDD2 + 32 VDD3 100 nF 19 VDD_XTAL 100 F (6.3 V) BLM32A07 +5 V 100 nF 18 VSS_XTAL 6 VSS1 11 VSS2 31 VSS3 100 F (6.3 V) 100 nF BLM32A07 +5 V
L DOLBY PRO LOGIC OR DOLBY 3 STEREO OR HALL/MATRIX OR INCREDIBLE SOUND C R SW
220
220
I2S_BCKIN2
27
data 1
DSP_RESET 470 pF TSCAN RTCB
17 AUTO BALANCE FUNCTION TEST +
13 3
22
FLAG TEST CONTROL
I2C BUS TRANSCEIVER
OSCILLATOR
7
8
9
10
15 SDA
16 SCL 10 220 k 10 k +5 V 100 pF 100 pF
14 A0
21 OSC
20 XTAL
4 SHTCB
DSP_IN1
DSP_OUT1 DSP_OUT2
DSP_IN2
220
4.7 H 100 k 10 pF 10 pF 1 nF
+5 V
Product specification
SAA7710T
MGE757
Fig.14 Application diagram.
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
PACKAGE OUTLINE SO32: plastic small outline package; 32 leads; body width 7.5 mm
SAA7710T
SOT287-1
D
E
A X
c y HE vM A
Z 32 17
Q A2 A1 pin 1 index Lp 1 e bp 16 wM L detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 0.02 0.01 c 0.27 0.18 0.011 0.007 D (1) 20.7 20.3 0.81 0.80 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 0.419 0.394 L 1.4 0.055 Lp 1.1 0.4 0.043 0.016 Q 1.2 1.0 0.047 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.95 0.55 0.037 0.022
0.012 0.096 0.004 0.086
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT287-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-25 97-05-22
1998 Mar 13
23
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering
SAA7710T
Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1998 Mar 13
24
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7710T
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 Mar 13
25
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
NOTES
SAA7710T
1998 Mar 13
26
Philips Semiconductors
Product specification
Dolby* Pro Logic Surround; Incredible Sound
NOTES
SAA7710T
1998 Mar 13
27
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
Internet: http://www.semiconductors.philips.com
SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545102/1200/04/pp28
Date of release: 1998 Mar 13
Document order number:
9397 750 03268

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